1. Field of the Invention
The present invention relates to random-access memory data paths and more specifically to the sense amplifiers for the static random-access memory data paths.
2. Art Background
A data path, such as the one shown in FIG. 1, in the static random-access memory (SRAM) architectural scheme has been well known in industry. Referring to FIG. 1, a symbolic representation of data path 10 for a typical SRAM is illustrated. Bit-line loads 100 are typically implemented in p-channel devices permanently enabled as will be appreciated by those skilled in the art. Coupled to bit-line loads 100 is data array 110. Charges stored in data array 110 are passed to path gates 120, typically implemented in n-channel devices for the write path and p-channel devices for the read path. Although not illustrated in FIG. 1, separate buses are implemented for both the write and read paths. Following pass gates 120 is the beginning of the sensing section of data path 10. Read/Write block 131 contains first sense amplifier 130, global data bus 132, second sense amplifier 140 and output buffer 150. An address transition detection circuit (ATD) 141 is used in data path 10 to produce appropriate pulses when word-line 114 switches, thus acting as a pseudo-clock signal. The ATD pulse, which is widely used in the SRAM industry, serves to equalize or reset voltage nodes between each access cycle. This kind of equalizing technique has been in use on nearly all fast SRAMs since 1984. However, as better and better performance is expected with each new generation of products, the circuitry required to generate the ATD pulse becomes more and more cumbersome and is in some cases the critical path for performance itself. It will be appreciated by those skilled in the art the disadvantages of the ATD system typically stem from large current spikes (when equalizing/resetting) and both process and floor-plan skewing of the ATD pulse. If the ATD pulse arrives too late or too early, too long or too short, it can destroy data or cause access delay.
Therefore, it is desirable to eliminate the need to equalize voltage levels between cycles and to detect the beginning of a new cycle. It is also desirable to reduce the circuitry required by an SRAM and to increase its performance, while shortening its design cycle.
As will be described in the following, the present invention achieves the objects by the use of two techniques. First, the voltage swing allowed on the output of the sense amplifier is reduced such that the recovery time between accesses is reduced. Second, the output voltages of the sense amplifiers are used in a cross-coupled formation to drive the tail devices to enhance the rate of change of the circuit.